Among the various genera of semiconductor data storage device technologies (“semiconductor memories” or simply “memories”), known-state and error detection/correction types are known. Error detection/correction types include parity and error correction code (“ECC”) memories. Today's compact computing devices (e.g., smart phones, tablet computers, industrial automation devices, automotive subsystems and the like) typically include one or both of the aforesaid memory types. Computing devices are increasingly imbedded in vehicles and other equipment to perform mission-critical functions such as vehicle steering, braking, anti-skid and even self-driving functions. An evolving set of functional safety standards increasingly mandate real-time testing of integrated circuit components imbedded in such mission-critical subsystems. In some cases test intervals referred to as fault tolerant time internals (“FTTIs”) are specified. Such intervals may be short relative to program code execution times (e.g., a few milliseconds).
Known-state memories include non-volatile technologies such as masked read-only memories (“ROMs”) and programmable read-only memories (“PROMs”) fabricated or programmed with a known data set. Known-state memories may also be implemented with memory technologies capable of being read from and written to during normal operation (“read/write” memories) but which retain their storage states during power-off conditions. So-called “flash” memory is an example of the latter type of memory. Even memories that are volatile at power-off may be known-state, to the extent that the latter memory types are written to with known data sets during operation.
Known-state memories are written with information intended by system design to remain unchanged during normal system operation. For example, industrial automation and automotive subsystems may include one or more blocks of known-state memory designed to store programmatic instructions associated with the core operating system, timing critical code and the like. One characteristic of a known-state block of memory is that the contents of the block may be represented by a predetermined value of one or a few memory words resulting from a calculation performed on the contents of the block. Such calculations include the well-known checksum calculation and variants of the well-known cyclic redundancy check (“CRC”) calculation method. A real-time test of the integrity of a known-state memory block may be performed by reading the block word-by-word, performing an incremental CRC calculation after reading each word, and comparing the final CRC calculation to the predetermined CRC value.
Parity and ECC memories include one or more reserved bits appended to each memory word. The appended bits are not generally available programmatically to an operating system or to a computer user. Rather, memory controller hardware performs a real-time logical calculation on each data word to be written to determine the state of the parity or ECC bit(s). The memory controller then writes both the data word and the parity/ECC bits corresponding to the binary value of the data word as determined by the real-time logical calculation. In the single-bit parity case, the memory controller is configured to operate with either even or odd parity. Operating with even parity, for example, the memory controller sets the parity bit if a parity calculation on the data word, excluding the parity bit, determines that the data word is of odd parity. Doing so causes the complete word, data plus parity bit, to be even. If the data word to be written were of even parity, the memory controller would reset the parity bit in order to maintain even parity.
When the memory is accessed, the memory controller expects to see the configured parity state across any data word read and that word's corresponding parity bit, given that the controller imposes the configured parity state on all words written to the memory by controlling the state of the parity bit. If the controller detects a parity state opposite the configured operating parity regimen, the controller generates an interrupt to the CPU to flag a memory error.
It is noted that such single-bit parity schemes are capable of detecting single-bit errors in a given data word. Two errors in a data word results in the latter word being read with the configured parity state and would thus go undetected. A block of deteriorating memory typically, but not always, exhibits increasing numbers of bad (e.g., “stuck”) bits with the passage of time. Consequently, the more frequently a particular memory address is read, the more likely the parity integrity check system will catch and flag single-bit errors. If an address is accessed infrequently, the more likely the memory cells corresponding to that address will have experienced a double-bit error that would go undetected with a simple parity integrity check regimen.
ECC memories operate with a similar detection system as described above for parity memory but with multiple integrity check bits appended to the data word. Consequently, ECC memories are able to detect a number of bit errors corresponding to the number of appended ECC bits. Some memory controllers also perform error correction operations using word data written redundantly to the ECC bit field. In either case, the principle of increasing the likelihood of detecting memory bit errors by increasing the frequency of accessing each memory block address holds for both parity and ECC memory error detection schemes.